Vertical MOSFETs and IGBTs are popular as high voltage, high power transistors due to the ability to provide a thick, low dopant concentration drift layer to achieve a high breakdown voltage in the off state. Typically, in an example of a MOSFET, the transistor includes a highly doped N-type substrate, a thick low dopant concentration N-type drift layer, a P-type body layer formed in the drift layer, an N-type source at the top of the body layer, and a gate separated from the channel region by a thin gate oxide. A source electrode is formed on the top surface, and a drain electrode is formed on the bottom surface. In an example of an IGBT, the N-type substrate is replaced with a P-type substrate. When the gate is sufficiently positive with respect to the source, the channel region of the P-type body between the N-type source and the N-type drift layer inverts to create a conductive path between the source (or emitter for an IGBT) and drain (or collector for an IGBT). For an IGBT, the initial current initiates regenerative action to turn on a vertical PNP bipolar transistor.
In the device's off-state, when the gate is shorted to the source or negative, the drift layer depletes, and high breakdown voltages, such as exceeding 600 volts, can be sustained between the source and drain. However, due to the required low doping of the thick drift layer, the on-resistance suffers. Increasing the doping of the drift layer, without increasing its thickness, reduces the on-resistance but lowers the breakdown voltage.
The Applicant had improved on the basic vertical MOSFET and IGBT structure and received U.S. Pat. No. 9,761,702 for such improvements. U.S. Pat. No. 9,761,702 is incorporated herein by reference and includes a detailed method for manufacturing such MOSFETs and IGBTs. In this present disclosure, Applicant further improves on the MOSFET and IGBT devices disclosed in U.S. Pat. No. 9,761,702.
FIG. 9A of Applicant's U.S. Pat. No. 9,761,702 is reproduced herein as prior art FIG. 1. FIG. 1 is believed to be the closest prior art for an IGBT embodiment. FIG. 1 is a cross-sectional view of a single vertical IGBT transistor cell (which may be a portion of a strip or a hexagonal cell) in an array of identical contiguous cells connected in parallel, where the gate 10 includes a vertical portion 12 surrounding a portion of a vertical side wall of a trench for improved on-resistance, and wherein a vertical shield field plate 14 is also in the trench for increasing breakdown voltage.
In one typical application, a load is connected between the bottom electrode 16 and a positive voltage supply, and the top emitter electrode 18 is connected to ground. The combination of the N++ and P regions connected to the electrode 18 are generally referred to as an emitter for the PNP transistor in an IGBT. The load may instead be connected between the emitter electrode 18 and ground. The emitter electrode 18 contacts the N++ emitter region 19. When a positive voltage is applied to the conductive gate 10 that is greater than the threshold voltage, the top surface of the P-well 20 is inverted and electrons accumulate along the vertical sidewalls of the N− layer 22 adjacent to the vertical extension 12 of the gate 10 to spread the current and lower the on-resistance of the N-layer 22.
A self-aligned enhanced N-surface region 24 (N-Surf) surrounds the edge of the P-well 20 and extends to the trench sidewall. The N-surface region 24 has a doping concentration that is higher than that of the N− layer 22. The vertical extension 12 of the gate 10 accumulates electrons in the N-surface region 24 to further lower its on-resistance. Therefore, the N-surface region 24 provides a lower on-resistance and better current spreading without adversely affecting the breakdown voltage.
A P+ contact region 26 ohmically connects the P-well 20 to the emitter electrode 18. The P+ contact region 26 and P-well 20 form part of the emitter.
A dielectric 28, such as oxide, insulates the emitter electrode 18 and the gate 10, and covers the trench sidewalls.
The N++ emitter region 19, the P-well 20, and the N− surface region 24 form a lateral DMOS transistor portion of the IGBT 30. In the on-state, there is a conductive channel between the emitter electrode 18 and the N− layer 22.
The combination of the lateral DMOS transistor portion, the higher doping of the N surface region 24, the vertical extension 12 of the gate 10, and the reduced thickness of the N—drift region 22/34/36 reduce the on-resistance and forward voltage drop. This structure also increases the breakdown voltage due to the effect of the vertical field plate 14 (connected to the emitter) and speeds up the switching time if the IGBT's internal PN diode becomes forward biased then reversed biased.
The vertical shield field plate 14, in combination with the vertical extension 12 of the gate 10, laterally depletes the N-layer 22 when the IGBT is off to improve the breakdown voltage. The entire N-layer 22 is preferably totally depleted at the onset of breakdown. The N--drift region 22/34/36 is preferably also totally depleted at the onset of breakdown.
The effect of the vertical extension 12 of the gate 10 (accumulates electrons along the sidewall) also allows a reduction of the P-well 20-to-trench spacing, enabling a reduction of the cell pitch and active area while still resulting in a lower on-resistance.
A self-aligned P-shield region 40 is formed below the trenches. In the off-state, the device is reversed biased and the P-shield region 40 lowers the electric field under the trench, since the P-shield region 40 is fully depleted prior to breakdown, which results in a higher breakdown voltage. The P-shield region 40 also serves to laterally deplete the N-layer 22 to further increase the breakdown voltage.
The P-shield region 40 can be floating, but to switch the device on from the off state, the parasitic capacitor resulting from the depletion layer between the P-shield region 40 and N-layers 22 and 34 has to be discharged. Therefore, for a MOSFET, it is preferable to connect the P-shield region 40 to the emitter electrode 18 via the P-well 20 and a P-type connection region in certain locations of the die (not shown). The connection of the P-shield region 40 to the emitter electrode 18 provides a path for current to discharge the capacitor and improves the switching delay during switching the device from the off to the on state. In the case of an IGBT (uses a P+ substrate), since the holes can be supplied through the backside P+ collector (P+ substrate), the effect of the floating P-shield region 40 on switching-off is reduced significantly.
P and N charge balance columns 44 and 46 lower the specific on-resistance (Rsp). The N columns 46 are more highly doped than the N-layer 22 so help reduce on-resistance. The N and P columns 46/44 deplete when the device is off and are preferably fully depleted, along with the P-shield region 40, at the onset of avalanche breakdown.
If the bottom semiconductor of the structure is an N++ substrate, the device is a vertical MOSFET. If the substrate 50 is a P++ type, as shown, the device is an IGBT, which lowers on-resistance at the expense of switching speed. In such a case, the drain electrode 16 becomes an anode or collector electrode. Turning on the IGBT by applying a threshold voltage to the gate 10 turns on the PNP transistor.
Although the device of FIG. 1, whether formed as a MOSFET or IGBT has world-class operating characteristics, there is still a desired to further improve performance.